The present disclosure relates to power supply interconnect structures of semiconductor integrated circuits in which power supply interconnects located in different interconnect layers are electrically connected by vias.
Conventionally, in a semiconductor integrated circuit, a power supply interconnect structure using a multi-stack via is known as a structure in which two power supply interconnects located in two different interconnect layers are electrically connected by a via. The conventional power supply interconnect structure will be described with reference to FIG. 11.
FIG. 11 is a cross-sectional view of an LSI interconnect layer, and FIG. 13 is a top view of the LSI interconnect layer. In these figures, L1-L4 denote first to fourth interconnect layers. Reference character 51 denotes a first power supply interconnect located in the first interconnect layer L1, reference character 52 denotes a fourth power supply interconnect located in the fourth interconnect layer L4. When connecting the first power supply interconnect 51 to the fourth power supply interconnect 52 as a single power supply interconnect, the second interconnect 53 and the third interconnect 54 for connecting the power supply interconnects 51 and 52 in the second and third interconnect layers L2 and L3. A first to third vias 56, 57, and 58 are located in three insulating layers I1-I3. The second and third interconnects 53 and 54 and the first to third vias 56-58 have the forms shown in the top view of FIG. 13. The vias 56-58 are multiple vias (double vias in the figure) in which two vias are closely arranged in a vertical direction in FIG. 13. The interconnects 53 and 54 connected to the multiple vias are widely formed in vertical and horizontal directions to include the double vias inside when viewed from the top.
As can be seen from FIG. 11, the first via 56, the second interconnect 53, the second via 57, the third interconnect 54, and the third via 58 in a single vertical line are stacked to form a single multi-stack via in the same vertical line. Using this multi-stack via as a single unit, five units are formed in the figure. There units connect the first power supply interconnect 51 to the fourth power supply interconnect 52, thereby forming an electrically connected single power supply interconnect.
Furthermore, Japanese Patent Publication No. 2003-86681 teaches calculating the amount of a current flowing between the first and second power supply interconnects 51 and 52, calculating the minimum number of necessary units from the amount of the current, and cutting unnecessary vias to increase interconnect resources. As exemplified by FIG. 11, in Japanese Patent Publication No. 2003-86681, a signal interconnect 62 of the second interconnect layer L2 is located between each two of the five units. This structure increases interconnection efficiency to improve interconnection characteristics.
Different from the above-described power supply interconnect structure, borderless vias have been developed as an interconnect structure of signal interconnects as shown in SEMI Japan, Text Book of Semiconductor Process, pp. 362-363. Like the multiple via shown in FIG. 13, the borderless vias do not have pad portions, which are excessive wide interconnect regions, and are the mainstream of a design for manufacture (DFM). With the development of manufacturing processes of semiconductors, vias and interconnects can be accurately formed in predetermined positions. Thus, a borderless vias is set so that the horizontal and vertical lengths are substantially equal to the horizontal and vertical lengths of an interconnect to which the borderless via is connected.